verilog.vams Files Deleted By Check and Save

verilog.vams files in the schematic cellview directory get deleted by check and save causing svn problems

If a schematic cellview contains a verilog.vams file, by default it will be deleted (without notifying VersIC) during Check and Save, and will appear to be missing to VersIC

Later versions of VersIC (1.6.150 and up) will automatically detect this problem and delete the file in DM, but this may not be what you want. 

Other options

Turn on AMS netlist creation

There is a Cadence setting which controls the creation of the verilog.vams file during Check and Save:

Under CIW->Tools->AMS->Options ... Generate AMS netlist, check the box. This is equivalent to:

amsDirect.vlog checkAndNetlist boolean t

and means that the file will be regenerated during Check and Save.

If 'checkAndNetlist' is nil, verilog.vams will not be regenerated and will be deleted if it exists, causing the missing file problem.

Selectively exclude schematic/verilog.vams files

If you don't care about schematic verilog.vams files, you can set the svn:ignore property on the schematic directories so that verilog.vams will not be managed:

Unix> find . -type d -name schematic | xargs svn propset svn:ignore verilog.vams

Use ASSIGN

Alternatively, use the ASSIGN mechanism in the cds.lib to have AMS create data outside the library:

1. Create a tmp directory for the library (e.g. ./<library>_tmp)
2. In the cds.lib file, associate the library with the tmp dir.

    ASSIGN <library> TMP ./<library>_tmp

With these settings, the verilog.vams and ams_direct.dat files are created in 
<library>_tmp/<cell>/schematic rather than in the real library. 
Edits to the schematic do not use the ASSIGNed area.

A complete description of the Cadence AMS variables is in the Cadence documentation available in your Cadence installtion or on SourceLink (search for 'amsenvug')